Sensitivity Analysis of Locked Circuits

15 pages•Published: May 27, 2020

Joseph Sweeney, Marijn J. H. Heule and Lawrence Pileggi

Abstract

Globalization of integrated circuits manufacturing has led to increased security con- cerns, notably theft of intellectual property. In response, logic locking techniques have been developed for protecting designs, but many of these techniques have been shown to be vulnerable to SAT-based attacks. In this paper, we explore the use of Boolean sensi- tivity to analyze these locked circuits. We show that in typical circuits there is an inverse relationship between input width and sensitivity. We then demonstrate the utility of this relationship for deobfuscating circuits locked with a class of “provably secure” logic lock- ing techniques. We conclude with an example of how to resist this attack, although the resistance is shown to be highly circuit dependent.

Keyphrases: boolean sensitivity, electronic circuits, logic locking, satisfiability

In: Elvira Albert and Laura Kovacs (editors). LPAR23. LPAR-23: 23rd International Conference on Logic for Programming, Artificial Intelligence and Reasoning, vol 73, pages 483-497.

Links:	https://easychair.org/publications/paper/HHHP
	https://doi.org/10.29007/7tpd

BibTeX entry

@inproceedings{LPAR23:Sensitivity_Analysis_Locked_Circuits,
  author    = {Joseph Sweeney and Marijn J. H. Heule and Lawrence Pileggi},
  title     = {Sensitivity Analysis of Locked Circuits},
  booktitle = {LPAR23. LPAR-23: 23rd International Conference on Logic for Programming, Artificial Intelligence and Reasoning},
  editor    = {Elvira Albert and Laura Kovacs},
  series    = {EPiC Series in Computing},
  volume    = {73},
  publisher = {EasyChair},
  bibsource = {EasyChair, https://easychair.org},
  issn      = {2398-7340},
  url       = {/publications/paper/HHHP},
  doi       = {10.29007/7tpd},
  pages     = {483-497},
  year      = {2020}}

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