Testing Arithmetic Circuits: Full Adder Based Circuits

EasyChair Preprint 15536

Abstract

In  this research paper,  it  is  reasoned  that  for  a  single  full  adder ( 1-bit  full  adder), the  sum and  carry  outputs  are  permutation  invariant in  the  three  input  variables. Further,  for  2-bit  full  adder  and  arbitrary  N-bit  full  adder,  the  sum  and  carry  outputs  are  partially  invariant  in  the  input  variables.These  results  enable  reducing  the number  of  input    combinations  (from  truth  table )  for  which  the  1-bit/N-bit  full  adder  needs  to  be  tested ( for  correctness )

Keyphrases: Full Adder, Partial Symmetric Functions, Symmetric Fujnctions, Testing ICs, Truth table

@booklet{EasyChair:15536,
  author    = {Rama Murthy Garimella and C.V. Vismay},
  title     = {Testing Arithmetic Circuits: Full Adder Based Circuits},
  howpublished = {EasyChair Preprint 15536},
  year      = {EasyChair, 2024}}