FinFET Based Disturbance Free SRAM Cell Design on 45nm Node with the Effect of Line Modulation

EasyChair Preprint 6201

Abstract

In the present scenario, we have great emphasis on high performance and low power in the designing of the memory circuits. The SRAM cell plays an important role in high-performance memory devices. On-chip integration of SRAM, server serious design challenges in terms of cell stability and power dissipation. An 8T SRAM cell at a 45 nm size in Fin-based transistors is proposed to achieve improvement in performance, stability and power dissipation compared with the previous designs for the low-performance circuit. In order to reduce the leakage power, the supply voltage is reduced to the threshold voltage of the cell transistor. This reduction in the threshold voltage of the cell also reduces the Static Noise Margin (SNM) of the SRAM cell. This reduced SNM is responsible for SRAM stability. By employing the proposed 8T circuit, high SNM is achieved in the operation of SRAM memory compared with a CMOS-based 6T SRAM design. In this paper, we propose a methodology and optimize FinFET devices for stable and low-power SRAMs. The 8T SRAM cell provides a much greater enhancement instability by eliminating cell disturbance during read access. The proposed design using FinFET shows less sensitivity to variation and also an improvement of 2.7× in reading static noise margin at V_DD = 0.7 V over bulk CMOS based SRAM cell. This paper also shows the effect of line voltage modulation on FinFET based 8T SRAM cells.

Keyphrases: 8T SRAM, Cell disturbance, FinFET, Line voltage modulation., stability

@booklet{EasyChair:6201,
  author    = {Vishal Gupta},
  title     = {FinFET Based Disturbance Free SRAM Cell Design on 45nm Node with the Effect of Line Modulation},
  howpublished = {EasyChair Preprint 6201},
  year      = {EasyChair, 2021}}