Sharing AES Engine for RISC-V Custom Instructions Performing Encryption and Decryption

EasyChair Preprint 15553

Abstract

In light of the critical role of cryptography in safeguarding data and the advantages of AES for hardware implementation, this paper presents a hardware implementation of the 128-bit Advanced Encryption Standard (AES) algorithm. We designed an AES unit that utilizes the same hardware for both encryption and decryption, which we integrated into a RISC-V-based processor, by developing four custom instructions to facilitate this integration. Our methodology leverages the inherent parallelism of the AES algorithm to optimize speed, enhance security features, and ensure low power consumption along with efficient resource utilization. A comprehensive performance analysis showed a nearly 19x speedup compared to a software implementation, demonstrating significant performance and efficiency benefits.

Keyphrases: AES decryption, AES encryption, Custom Instruction, FPGA Hardware Implementation, RISC-V processor Security

@booklet{EasyChair:15553,
  author    = {Zahra Hojati and Zahra Jahanpeima and Maryam Rajabalipanah and Hossein Ta'Ati and Atefe Rabiei and Zain Navabi},
  title     = {Sharing AES Engine for RISC-V Custom Instructions Performing Encryption and Decryption},
  howpublished = {EasyChair Preprint 15553},
  year      = {EasyChair, 2024}}